Design and Implementation of High-speed Asynchronous Communication Ports for Vlsi Multicomputer Nodes †

A communication coprocessor that provides highbandwidth low-latency inter-node communication is a key component of multicomputer systems composed of hundreds of computing nodes interconnected by point-to-point links. For high reliability, interdependency between nodes is minimized by using a separate clock at each node. Thus, the coprocessor must handle asynchronous inputs with a very low probability of synchronization failures. In order to minimize system chip count, the entire coprocessor should be implemented on a single CMOS VLSI chip. Thus, limitations on the raw speed and pin drive capabilities of this technology must be considered. This paper discusses the design and implementation of communication ports for a communication coprocessor chip. We describe several schemes for handling high-speed asynchronous communication and present a new design of a communication port that includes a synchronizer and a highperformance FIFO buffer. This design is particularly wellsuited for VLSI implementation and, for a given technology, can support higher communication speeds than previous synchronizer designs.